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At such high sampling rate, massively time-interleaved successive-approximation adc (sar adc) architecture has emerged as the dominant solution due to its excellent power efficiency several recent works has demonstrated success in achieving high sampling rate. Phd thesis presentation: a single channel high speed piplined sar adc with open-loop mdac by chao wu. Low power sar adc design background in wireless communication for wireless sensor nodes, the analog-to-digital converter (adc) is a mixed-signal bridge between the analog world (analog front-end) and the digital world (dsp) as shown in figure 1. Data converters for high speed cmos links a phd thesis high bandwidth sample-and-hold amplifiers are used in the adc, and this thesis is dedicated to my . Noise, speed, and power trade-offs in pipelined analog to digital converters phd thesis, university of california, berkeley (sar) analog-to-digital converter .
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